In recent years, various signal reading methods have been put forth for CMOS imaging sensors. In general, CMOS imaging sensors of a column-parallel-output type are often used. The CMOS imaging sensors select pixels of a row in a pixel array, and reads, in a column direction, signals generated in each of the pixels.
Out of such CMOS imaging sensors, a conventional imaging sensor disclosed in Patent Reference 1 will be described with reference to FIG. 1. FIG. 1 schematically illustrates a conventional CMOS solid-state imaging device (CMOS imaging sensor) including AD converting devices on a semiconductor substrate on which pixel units are arranged.
As illustrated in FIG. 1, the solid-state imaging device 1 includes: a pixel array (imaging unit) 10 that includes unit pixels 3 in rows and columns; a driving control unit 7 that is arranged outside the pixel array 10; a column processing unit 26 including column AD circuits 25 for each of the vertical columns; a reference signal generating unit 27 including a digital analog converter (DAC) 27a for supplying reference voltages for AD conversion to the column AD circuits 25 in the column processing unit 26; and an output circuit 28.
Furthermore, the driving control unit 7 includes: a horizontal scanning circuit (column scanning circuit) 12 for controlling a column address and scanning of a column; a vertical scanning circuit (row scanning circuit) 14 for controlling a row address and scanning of a row; and a communication/timing control unit 20 for receiving a master clock CLK0 through a terminal 5a, generating various internal clocks, and controlling, for example, the horizontal scanning circuit 12 and the vertical scanning circuit 14.
Furthermore, each of the unit pixels 3 is connected to a row control line 15 controlled by the vertical scanning circuit 14, and to a vertical signal line 19 through which a pixel signal is transmitted to the column processing unit 26.
Furthermore, each of the column AD circuits 25 includes a voltage comparator 252 that compares a reference voltage RAMP generated by the reference signal generating unit 27 with an analog pixel signal obtained through one of vertical signal lines 19 (H0, H1, . . . ) from one of the unit pixels 3, for each of the row control line 15 (V1, V2, . . . ); a data storing unit 256 that is a memory holding a result of counting by a counting unit 254 until the voltage comparator 252 completes the comparison processing, and has a n-bit AD conversion function.
Furthermore, the stepwise reference voltage RAMP generated in the reference signal generating unit 27 is fed to one input terminal RAMP of the voltage comparators 252, and a corresponding one of the vertical signal lines 19 is connected to the other one of the input terminals so that pixel signal voltages are respectively provided from the pixel array 10. Furthermore, an output signal of each of the voltage comparators 252 is supplied to a corresponding one of the counting units 254.
Furthermore, each of the column AD circuits 25 has a structure for allowing AD conversion by the processes of supplying the reference voltage RAMP to a corresponding one of the voltage comparators 252, simultaneously starting to count a clock signal, and comparing the reference voltage RAMP with the analog pixel signal fed through a corresponding one of the vertical signal lines 19, while the comparison continues until a pulse signal is obtained.
As well as the AD conversion, processing is performed on a pixel signal, in a voltage mode, provided through each of the vertical signal lines 19. The processing is for calculating a difference between a signal level (noise level) of the pixel signal immediately after a pixel is reset and an actual signal level Vsig of the pixel signal. The signal level Vsig corresponds to an amount of light incident on each of the unit pixels 3. With the processing, a noise signal component referred to as a Fixed Pattern Noise (FPN) or a reset noise can be removed. FIG. 1 illustrates the structure for extracting only the actual signal level Vsig by counting down the noise level and counting up the signal level.
Furthermore, the pixel data digitalized by each of the column AD circuits 25 is transmitted to a horizontal signal line 18, through a horizontal selection switch that is not illustrated and is driven by a horizontal selection signal from the horizontal scanning circuit 12, and further transmitted to the output circuit 28.
With the structure, the pixel signals are successively outputted for each of the rows and columns from the pixel array 10 in which light-receiving elements as charge generating units are arranged in a matrix. Then, an image corresponds to the pixel array 10 in which the light-receiving elements are arranged in the matrix, that is, a frame image is represented by a collection of the pixel signals in the entire pixel array 10.
Next, the detailed operations of the column AD circuits 25 included in the solid-state imaging device indicated as a conventional art will be described with reference to FIG. 1 and a timing chart in FIG. 3.
In the first read operation, the communication/timing control unit 20 resets a count value of each of the counting units 254 to an initial value “0”, and sets the counting units 254 to a down-count mode. After reading from each of the unit pixels 3 in any row Vx to a corresponding one of the vertical signal lines 19 (H1, H2, . . . ) becomes stable, the communication/timing control unit 20 supplies control data 4 for generating a reference voltage RAMP to the reference signal generating unit 27.
Upon receipt of the control data 4, the reference signal generating unit 27 supplies a staircase waveform (RAMP waveform) that temporally varies in a staircase manner on the whole, as a comparison voltage for the one input terminal RAMP of each of the voltage comparators 252. Each of the voltage comparators 252 compares the comparison voltage having the RAMP waveform with a voltage of a pixel signal, in any of the vertical signal lines 19 (Hx), to be supplied from the pixel array 10.
Furthermore, each of the counting units 254 measures a time period for comparison by a corresponding one of the voltage comparators 252 that are arranged in the columns, simultaneously when the reference voltage RAMP having the RAMP waveform is fed to the one input terminal RAMP of the corresponding one of the voltage comparators 252. In order to do so, the communication/timing control unit 20 supplies a count clock CK0 to a clock terminal of each of the counting units 254, and the counting units 254 start to count down the count clock CK0 from the initial value “0” as the first count operation, in synchronization with the transmission of the voltages having the RAMP waveform from the reference signal generating unit 27 (t10).
Furthermore, each of the voltage comparators 252 compares the reference voltage RAMP having the ramp waveform from the reference signal generating unit 27, with the pixel signal voltage Vx fed through a corresponding one of the vertical signal lines 19. When the voltages match with each other, the output level of the voltage comparators 252 is inverted from a high level to a low level (t12).
In other words, each of the voltage comparators 252 compares a voltage signal corresponding to a reset component Vrst with the reference voltage RAMP, and a corresponding one of the counting units 254 measures a magnitude of the reset component Vrst using the count clock CK0 in a time axis direction to obtain a count value corresponding to the reset component Vrst. In other words, each of the counting units 254 measures a time period from the change in the voltage comparator RAMP waveform (in other words, when each of the counting units 254 starts the counting process) to inversion of the output of a corresponding one of the voltage comparators 252, resulting in the count value corresponding to the reset component Vrst.
Furthermore, when a predetermined down-count period passes (t14), the communication/timing control unit 20 stops supplying (i) control data to the voltage comparators 252 and (ii) the count clocks CK0 to the counting units 254. Thereby, each of the voltage comparators 252 stops generating the reference voltage RAMP having the ramp waveform.
Since the count operation is performed with detection of a reset level Vrst in the pixel signal voltage Vx by the voltage comparators 252 in the first read operation, a reset component ΔV of each of the unit pixels 3 is read.
Next, in the second read operation, the signal level Vsig corresponding to the amount of light incident on each of the unit pixels 3 and the reset component ΔV are read. The difference between the first and second read operations is that the counting units 254 are set to an up-count mode in the second read operation. Performing the second read operation in the same manner as that of the first read operation results in obtainment of a count value corresponding to the signal component Vsig.
In FIGS. 1 and 3, each of the counting units 254 performs the down-count operation in the first read operation, and the up-count operation in the second read operation. Thus, the counting units 254 automatically perform subtraction to obtain a count value corresponding to only the signal component Vsig, with respect to a count value “0”.    Patent Reference 1: Japanese Unexamined Patent Application Publication No. 2005-323331